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U2785B
DECT PLL / TX IC
Description
The U2785B is an RF IC for low-power DECT transmit applications. The SSO28-packaged IC is a complete PLL including a 1-GHz prescaler, on-chip frequency doubler, biasing for off-chip VCO, an integrated TX-filter and a modulation compensation circuit for advanced closedloop modulation concept. No mechanical tuning is necessary in production. Electrostatic sensitive device. Observe precautions for handling.
Features
D 1-GHz PLL, TX data filter (10.368-MHz / 20.736-MHz reference clock), frequency doubler D Low current consumption D Few external components D Supply-voltage range 2.7 V to 4.7 V D Switchable charge-pump current for enhanced switching time D Two operational amplifiers for active loop filter D Advanced closed-loop modulation (with 10.368-MHz / 20.736-MHz reference clock) and open-loop modulation supported
Block Diagram
FD_OUT1 FD_OUT2 CP REF_CLK
FD
RF_IN
CP 2f f
RC n
f
Bandgap
TX_DATA
PU OLE
Control logic
PC f n
PD
MCC
GF
GF_DATA LD
DAC
+ -
OP 1
+ -
OP 2 3-wire bus
DAC OP_REF_P
OP1_N
OP1_OUT
OP2_N
OP2_OUT CLOCK DATA ENABLE 14638
Figure 1. Block diagram
Ordering Information
Extended Type Number U2785B-MFS U2785B-MFSG3 Package SSO28 SSO28 Remarks Tube Taped and reeled
Rev. A4, 19-Jan-00
1 (14)
Preliminary Information
U2785B
Pin Description
CLOCK DATA ENABLE REF_CLK LD I_CP_SW 1 2 3 4 5 6 28 TX_DATA 27 PU 26 OLE 25 GND_D 24 DAC 23 RF_IN 22 GND_RF_IN
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND_FD_OUT 7 FD_OUT1 FD_OUT2 VS GF_DATA GND_CP VS_CP CP 8 9 10 11 12 13 14 Figure 2. Pinning
U2785B
21 VCO_BIAS 20 OP2_OUT 19 OP2_N 18 GND_OP 17 OP1_OUT 16 OP_REF_P 15 OP1_N
Function 3-wire bus: clock input 3-wire bus: data input 3-wire bus: enable input Reference frequency input Lock-detect output Charge-pump current switch Frequency doubler buffer ground Frequency doubler buffer output Supply voltage Modulation output GF_DATA (Gaussian-filtered data signal) GND_CP Charge-pump ground VS_CP Charge-pump supply voltage CP Charge-pump output Operational amplifier 1 invertOP1_N ing input Operational amplifier OP_REF_P reference voltage (internal) OP1_OUT Operational amplifier 1 output GND_OP Operational amplifier ground Operational amplifier 2 invertOP2_N ing input OP2_OUT Operational amplifier 2 output VCO_BIAS VCO bias voltage output GND_RF_IN RF input ground RF input from VCO to doubler RF_IN and PLL DAC DAC for VCO pretune GND_D Digital ground OLE Open-loop enable input PU Power-up input (active high) Digital TX data input to TX_DATA Gaussian filter and modulation-compensation circuit
Symbol CLOCK DATA ENABLE REF_CLK LD I_CP_SW GND_FD_ OUT FD_OUT1 FD_OUT2 VS
Functional Blocks
CP DAC FD GF OP1 OP2 Charge pump D/A converter for pretuning the VCO Frequency doubler Gaussian filter for transmit data 1st amplifier for loop filter 2nd amplifier for loop filter MCC PC PD RC VCO Modulation-compensation circuit Programmable counter = main counter (MC) + swallow counter (SC) Phase detector Reference counter Voltage-controlled oscillator
2 (14)
Rev. A4, 19-Jan-00
Preliminary Information
U2785B
Absolute Maximum Ratings
All voltages are referred to GND (Pins 7, 12, 18, 22 and 25) Supply voltage Logic input voltage Junction temperature Storage temperature Parameters Pins 10, 13 Pins 1, 2, 3, 6, 26, 27 and 28 Symbol VS VIN Tj Tstg Value 5.0 - 0.3 to VS 150 - 40 to +150 Unit V V C C
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 130 Unit K/W
Operating Range
All voltages are referred to GND (Pins 7, 12, 18, 22 and 25) Parameters Supply voltage Ambient temperature Symbol VS Tamb Min. 2.7 - 25 Typ. 3.0 +25 Max. 4.7 +85 Unit V C
Electrical Characteristics
Test conditions (unless otherwise specified) : VS = 3 V, Tamb = 25C Parameters Power supply Supply current Test Conditions / Pins Symbol Pin 10 VPU = low level = `0` IS,OFF RX (OLE = `1`) IS TX (OLE = `0`) IS TX, MCC ON IS TX, MCC, GF ON IS TX, MCC, GF, OP ON IS TX, MCC, GF, OP, FD ON IS VVS_CP = 3 V, ICP PLL in lock condition Pin 14 fRF_IN = 900 MHz PRF_IN = - 10 dBm, Zload = 50 O (differential), PFD_OUT Pins 8 and 9 (differential) PRF_IN = - 10 dBm, 2nd and 3rd, HS Pin 8 and 9 (differential) PRF_IN = - 10 dBm, SHS Pin 8 and 9 (differential) Pin 23 fRF_IN = 800 to 1000 MHz AC-coupled sine wave Pin 23 fRF_IN VRF_IN Min. Typ. 1 5.6 13 15 17 19 30 1 Max. 10 Unit mA mA mA mA mA mA mA mA
Supply current CP Frequency doubler Output power Harmonic suppression Subharmonic suppression PLL Input frequency Input voltage
- 10 - 20 - 20 800 20
-5
-3
dBm dBc dBc
1000 200
MHz mVrms
Rev. A4, 19-Jan-00
3 (14)
Preliminary Information
U2785B
Electrical Characteristics (continued)
Test conditions (unless otherwise specified) : Vs = 3 V, Tamb = 25C Parameters Test Conditions / Pins Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter Scaling factor reference Pin 4 counter External reference input AC-coupled sine wave frequency Pin 4 External reference input AC-coupled sine wave voltage Pin 4 Charge pump, active when RX, TX Pin 14 CPCS = 100%, VI_CP_SW = '0`, Output current VCP = VVS_CP / 2 CPCS = 100%, VI_CP_SW = '1`, VCP = VVS_CP / 2 Current scaling factor See bus protocol D0...D2 ICP = CPCSxICP_NOM Leakage current Operational amplifiers 1 and 2 Power gain bandwidth Pins 17 and 20 Excess phase Rload = 1 kO, Cload = 15 pF Pins 17 and 20 Input offset voltage Pins 15, 16 and 19 Open-loop gain Pins 17 and 20 Output-voltage range Pins 17 and 20 Common-mode input Pins 15, 16 and 19 voltage Modulation-compensation circuit @ max. DSV 64 Oversampling fREF_CLK = 10.368 MHz or fREF_CLK = 20.736 MHz Integration counter Current scaling factor See bus protocol E3 ... E5 Gaussian transmit filter (Gaussian shape B x T = 0.5) fREF_CLK = 10.368 MHz, TX, TX data filter clock 18 taps in filter, SRC = 12 fREF_CLK = 20.736 MHz, TX, 18 taps in filter, SRC = 24 Maximum output current Polarity see bus protocol D13, GFCS = 100%, Pin 11 Current scaling factor See bus protocol D6 ... D8 IGF_DATA = GFCSxIGF_NOM Pin 11 Symbol SPSC SMC SSC SRC fREF_CLK VREF_CLK Min. 0 5 50 12/16/ 24 10.368 20.736 Typ. 32/33 31/32/ 33/34 Max. 31 22 250 MHz mVrms mA mA 130 100 10 80 1 70 0.3 0.3
VS - 0.3 VS - 0.3
Unit
ICP_NOM1 ICP_NOM5
?1 ?5 60
CPCS ICP_O PGBW d Voffs g Vout Vin OVS MAC MCCS
% pA MHz degree mV dB V V
-
9
576 130 % MHz MHz mA 130 %
- 576 60 fREF_CLK has to be chosen fTXFCLK fTXFCLK
|IGF_NOM|
-
10.368 10.368 80
GFCS
60
4 (14)
Rev. A4, 19-Jan-00
Preliminary Information
U2785B
Electrical Characteristics (continued)
Test conditions (unless otherwise specified) : Vs = 3 V, Tamb = 25C Parameters VCO biasing Pin 21 Bias voltage Test Conditions / Pins Symbol Min. Typ. Max. Unit
VVCO 1.5 V Standby, PU = '0` VVCO_O 10 mV Temperature coefficient TCVCO - 3.3 mV/K DAC for VCO pretune, 3-bit programming, see bus protocol D3 ... D5 Pin 24 DAC low level Iload = 1 mA VDAC_min 0.3 V DAC step level Iload = 1 mA VDAC_step 0.3 V DAC high level Iload = 1 mA VDAC_max 2.3 V Output impedance RDAC_out 10 kO Lock-detect and test-mode output Pin 5 Lock-detect output Locked = '1` LD unlocked = '0` Test-mode output Test modes see bus protocol LD E0 ... E2 Leakage current VOH = 4.5 V ILD_O 5 mA VLD_min Saturation voltage IOL = 0.5 mA 0.4 V 3-wire bus Pin 1 Clock fclock 1.152 MHz Logic input levels (CLOCK, DATA, ENABLE, I_CP_SW, OLE, GF_DATA) Pins 1, 2, 3, 6, 26 and 28 High input level = '1` ViH 1.5 V Low input level = '0` ViL 0.5 V High input current = '1` IiH -5 5 mA Low input current = '0` IiL -5 5 mA Standby control Pin 27 Power-up high input level PU = '1` VPU 2.0 V Power-up low input level PU = '0` (standby) VPU_O 0.7 V Power-up high input VPU = 3 V, PU = '1` 100 125 150 IPU mA current VPU = 4.5 V 220 300 420 Power-up low input VPU = 0 V, PU = '0` 0.1 IPU_O mA current VPU = 0.5 V 1 Settling time Switched from tsoa 10 ms VS = 0 - > active operation VS = 0 to VS = 3 V Settling time Switched from standby to tssa 10 ms standby- > active operation PU = '1` Settling time Switched from tsas 2 ms active operation- > standby PU = '1` to standby -
Rev. A4, 19-Jan-00
5 (14)
Preliminary Information
U2785B
PLL Principle
RF_IN Programmable counter PC: (main counter MC + swallow counter SC)
fLO = fRCx(SMCx32 + SSC)
fLO
fPC Phase frequency detector PD ICP Loop filter VCO Frequency doubler FD 2xfLO
FD_OUT
fRC = 0.864 MHz
DAC
GF_DATA
Controlled phase shifting
Modulation compensation MCC
Gaussian filter GF
Reference counter RC REF_CLK 10.368 MHz 13.824 MHz* 20.736 MHz SRC 12 16 24 10.368 MHz
* MCC and GF not possible
1.152 Mbit/s
PLL reference frequency REF_CLK
TX_DATA
Baseband controller
14639
Figure 3. PLL principle
6 (14)
Rev. A4, 19-Jan-00
Preliminary Information
U2785B
The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for an optional DECT band extension. Intermediate frequencies of 110.592 and 112.32 MHz are supported. Mode TX fIF MHz Channel CO C1 C2 C3 C4 C5 C6 C7 C8 C9 110.592 CO C1 C2 C3 C4 C5 C6 C7 C8 C9 CO C1 C2 C3 C4 C5 C6 C7 C8 C9 fANT MHz 1897.344 1895.616 1893.888 1892.16 1890.432 1888.704 1886.976 1885.248 1883.52 1881.792 1897.344 1895.616 1893.888 1892.16 1890.432 1888.704 1886.976 1885.248 1883.52 1881.792 1897.344 1895.616 1893.888 1892.16 1890.432 1888.704 1886.976 1885.248 1883.52 1881.792 fLO MHz 948.672 947.808 946.944 946.08 945.216 944.352 943.488 942.624 941.76 940.896 893.376 892.512 891.648 890.784 889.92 889.056 888.192 887.328 886.464 885.6 892.512 891.648 890.784 889.92 889.056 888.192 887.328 886.464 885.6 884.792 2fLO MHz 1897.344 1895.616 1893.888 1892.16 1890.432 1888.704 1886.976 1885.248 1883.52 1881.792 1786.752 1785.024 1783.296 1781.568 1779.84 1778.112 1776.384 1774.656 1772.928 1771.2 1785.024 1783.296 1781.568 1779.84 1778.112 1776.384 1774.656 1772.928 1771.2 1769.472 SMC 34 34 34 34 34 34 34 34 34 34 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 SSC 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 1 0
RX
112.32
Limits Mode TX RX TX RX fIF MHz fmin 110.592 112.32 fmax 110.952 112.32 fANT MHz 1714.176 1824.768 1826.496 1933.632 2044.224 2045.952 fLO MHz 857.088 857.088 857.088 966.816 966.816 966.816 2fLO MHz 1714.176 1714.176 1714.176 1933.623 1933.623 1933.623 SMC 31 31 31 34 34 34 SSC 0 0 0 31 31 31
Rev. A4, 19-Jan-00
7 (14)
Preliminary Information
U2785B
Formulas fANT C1 - fANT C2 = 1.728 MHz for TX: fLO = fANT / 2 for RX: fLO = (fANT - fIF) / 2 SMC = integer (fFD / 0.864 MHz / 32) SSC = MOD ((fFD / 0.864 MHz) / 32)
Serial Programming Bus
Reference and programmable counters can be programmed by the 3-wire bus (CLOCK, DATA and ENABLE). Besides this information, additional control bits as phase-detector polarity and scaling of charge-pump currents as well as internal currents for Gaussian lowpass filter and modulation-compensation circuit can be transferred. After setting the enable signal to low condition, the data status is transferred bit-by-bit on the rising edge of the clock signal into the shift register, starting with the MSB bit. When the enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address-bit condition (last bit). Additional leading bits are ignored and there is no check carried out how many pulses arrived during enable low condition. The bus then returns to low-current standby mode until the enable signal changes to low again. During standby of the PLL, the information in the registers of the PLL is not maintained.
Control Signals
I_CP_SW LD input for switching charge-pump current by factor 5 output which is active after PLL is locked and test-mode output (according to programmed test mode) enable input for open-loop modulation DAC for VCO band switch hardware power-up / standby of complete PLL / TX IC
OLE DAC PU
Bus Protocol Formats
MSB Data bits D22 0 D21 1 D20 0 D19 1 D18 SC 0 1 0 1 D17 D16 D15 D14 1 D13 0 D12 PS 0 0 D11 D10 GF 1 D9 MCC 1 1 D8 D7 GFCS 0 FD 0 OP 1 1 1 D6 D5 D4 DAC 1 MCCS 0 0 0 1 1 D3 D2 D1 CPCS 0 TEST 0 0 0 D0 LSB Address bit A0 1 1 0 0
RC
MC
Standard bit setting:
word 1 word 2
1
PLL Settings
RC (Reference Divider) D22 0 0 1 1 D21 0 1 0 1 SCR 12 16 24 0 0 1 1 MC (Main Divider) D15 D14 0 1 0 1 SMC 31 32 33 34 D20 0 0 0 0 1 1 1) D19 0 0 0 0 1 1 SC (Swallow Counter) D18 0 0 0 0 1 1 D17 0 0 1 1 1 1 D16 0 1 0 1 0 1 SSC 1) 0 1 2 3 30 31
SPGD = 32xSMC + SSC
SSC = [D16]x20 + [D17]x21 + .... + [D20]x24
8 (14)
Rev. A4, 19-Jan-00
Preliminary Information
U2785B
Phase Settings
Phase of GF_DATA D13 0 1 GF_DATA Source Sink Phase of MCC Internal Connection D12 1 0 MCC_DATA Normal Inverted D11 1 0 Phase of CP (Charge Pump) fR > fP ISource ISink fR < fP ISink ISource fR = fP High imp. High imp
Current-Saving Power-up/ down Settings
D10 0 1 GF (Gaussian Filter) off on D9 0 1 MCC (ModulationCompensation Circuit) off on E7 0 1 FD (Frequency Doubler) off on E6 0 1 OP1 + OP2 (Op Amps) off on
Current Gain Settings
GFCS (Gaussian-Filter Current Settings) D8 0 0 0 0 1 1 1 1 D7 0 0 1 1 0 0 1 1 D6 0 1 0 1 0 1 0 1 GFCS 60% 70% 80% 90% 100% 110% 120% 130% D2 0 0 0 0 1 1 1 1 CPCS (Charge-Pump Current Settings) D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 CPCS 60% 70% 80% 90% 100% 110% 120% 130%
MCCS (Modulation-Compensation Current Settings) E5 0 0 0 0 1 1 1 1 E4 0 0 1 1 0 0 1 1 E3 0 1 0 1 0 1 0 1 MCCS 60% 70% 80% 90% 100% 110% 120% 130%
Pretune DAC Voltage Settings
Pretune DAC Voltage D5 0 0 0 0 1 1 1 1 D4 0 0 1 1 0 0 1 1 D3 0 1 0 1 0 1 0 1 DAC 0.3 V 0.6 V 0.9 V 1.2 V 1.4 V 1.7 V 2.0 V 2.3 V D11 x 0 1 x x 0 1 x E2 0 0 0 0 1 1 1 1 E1 0 0 1 1 0 0 1 1
Test Mode Settings
Test Output Pin LD (Lock Detect) E0 0 1 0 1 0 1 0 1 Signal at Lock Detect Output Lock detect RC out PC out RC out div. by 2048 (MCCTEST) CP tristate only RC out PC out RC out div. by 2 (GFTEST) CP Mode Active Active Active Active High impedance High impedance High impedance High impedance
Rev. A4, 19-Jan-00
9 (14)
Preliminary Information
U2785B
3-Wire Bus Protocol
DATA CLOCK ENABLE
TL TS TC TH TEC TED TT
14641
MSB
LSB
Figure 4. 3-wire bus protocol timing diagram
Parameters Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to clock Hold time enable to data Time between two protocols
Symbol TS TH TC TL TEC TED TT
Min. Value 434 0 434 217 0 0 868
Unit ns ns ns ns ns ns ns
Typical Application Circuit
VCO
OLE PU TX_DATA
Loop filter LF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Control logic
PC
DAC
PD OP2 OP1
f
n
MCC
PLL/TX U2785B
3-wire bus 1
CLOCK DATA ENABLE REF_CLK LD I_CP_SW
n f 3 4
RC
FD
2f 8
f
GF
Bandgap 10 11 12
CP
2
5
6
7
9
13
14
VS FD_OUT1 FD_OUT2
14642
Figure 5. Typical application circuit
10 (14)
Rev. A4, 19-Jan-00
Preliminary Information
U2785B
Input / Output Interface Circuits
VS VS
10k 1, 2, 3, 6, 26, 28 5k (10k) 5k (10k) 4 REF_CLK
10k
14643
14644
Figure 6.
Figure 9.
VS 5 LD
100
8, 9 FD_OUT1 FD_OUT2
14645
7 GND_FD_OUT
14646
Figure 7.
Figure 10.
13 VS_CP
VS
11 GF_DATA
14 CP
12
14647
GND_CP
14648
Figure 8.
Figure 11.
Rev. A4, 19-Jan-00
11 (14)
Preliminary Information
U2785B
Input / Output Interface Circuits (continued)
VS VS
1k 15, 19 OP1_N OP2_N 16 OP_REF_P
21 VCO_BIAS
18 GND_OP
14649 14652
Figure 12.
VS
Figure 15.
VS
ABcontrol
17, 20 OP1_OUT OP2_OUT 10k 18 GND_OP
14651
24 DAC
14654
Figure 13.
VS
20k
Figure 16.
10k 10k
140k
1.5k 23 RF_IN
1.5k
27 PU
10k
25k
25k
22 GND_RF_IN
14653
14655
Figure 14.
Figure 17.
12 (14)
Rev. A4, 19-Jan-00
Preliminary Information
U2785B
Input / Output Interface Circuits (continued)
VS 10 VS_CP 13 GND_FD_OUT 7 GND_CP 12 GND_OP 18 GND_RF_IN 22 GND_D 25
14656
Figure 18.
Package Information
Package SSO28
Dimensions in mm
9.10 9.01 5.7 5.3 4.5 4.3
1.30 0.25 0.65 8.45 15 0.15 0.05 0.15 6.6 6.3
28
technical drawings according to DIN specifications
13018
1
14
Rev. A4, 19-Jan-00
13 (14)
Preliminary Information
U2785B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic- semi.com -
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
14 (14)
Rev. A4, 19-Jan-00
Preliminary Information

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